When a software program runs on a computer, the computer downloads instructions and data from a disk or hard drive and stores some data in a memory device under the direction of a microprocessor. In recent years, many advances in computer technology have increased the speed of both memory devices and microprocessors. Further, the size and complexity of software programs such as word processors, spread sheets and operating systems has increased dramatically. Thus, it is common for a computer user to purchase and install additional memory devices to a computer after a period of time to avoid the expense of buying a new computer. Unfortunately, the expanded memory increases the load on control lines in the computer from the microprocessor to the memory devices and can adversely affect transition times for control signals, thus preventing proper operation of the memory devices.
In dynamic random access memory (DRAM) devices, for example, a control signal is used in receiving the address of a memory cell from the microprocessor of the computer. A DRAM device stores data in memory cells arranged in an array of rows and columns. To read data from or write data to a memory cell, a processor provides the address of the desired memory cell to the DRAM device. The address contains at least two pieces of information: the row and the column of the desired cell. The processor informs the DRAM device when the row address is ready to be used by the DRAM device by bringing a control signal, referred to as Row Address Strobe ("RAS"), to a specified logic level. The processor then uses a second control signal, referred to as Column Address Strobe ("CAS"), to inform the DRAM device when the column address is ready to be used by the DRAM device. To increase the speed of DRAM devices, many DRAM devices successively access cells in the same row using a pulse train for the CAS control signal. DRAM manufacturers specify acceptable pulse widths for CAS control signals used with their memory devices. The CAS control signal provided to a DRAM device may not meet these specifications because the width of the pulse may be too short in either the high or low logic levels due to higher speeds of processors and the load created by expanded memory. Thus, the DRAM device will not function properly.
There is a need in the art for a memory device that operates properly irrespective of the load on the control lines from the microprocessor.